Pocket Developer Tech Specs• Altera Cyclone V FPGA with 49K logic elements & 3.4mbit BRAM • Altera Cyclone 10 with 15k logic elements • 2x Cellular RAM 16Mbyte for a total of 32mbyte low latency memory • Each independently addressable • 16 bit data bus width • 1x Synchronous DRAM 64Mbyte with a data bus width of 16 bits • 1x Asynchronous SRAM 256Kbyte with a data bus width of 16 bits